verilog how to create linear feedback shift register

Assertion of the Active High 'Load' signal at the rising edge of a clock will load the seed value into the LFSR.īefore the LFSR is used for the first time, the Active Low 'Reset' must first be asserted to initialize the Taps lookup table. The parallel 'seed' input port (same length as the bit width) can be used to start the LFSR sequence at a certain position in the pseudo-random sequence. The VHDL entity can be instantiated with an LFSR bit width of 2 to 32. The implemented LFSR is coded for maximal length (2 N-1), where N is the number of bits in the LFSR. Optimum Tap Points for Maximal Length Sequences The following table shows a minimum number of taps that yield maximal length sequences for LFSRs ranging from 2 to 32 bits. Certain tap settings yield the maximal length sequences of (2 N-1). The choice of which taps to use determines how many values are included in a sequence of pseudo-random values before the sequence is repeated. The implemented LFSR uses a one-to-many structure, rather than a many-to-one structure, since this structure always has the shortest clock-to-clock delay path.Ī diagram of an eight bit LFSR is as follows: The choice of taps determines how many values there are in a given sequence before the sequence repeats. It is this feedback that causes the register to loop through repetitive sequences of pseudo-random value. Register bits that do not need an input tap, operate as a standard shift register. This is a PDF file.įeedback around an LFSR's shift register comes from a selection of points (taps) in the register chain and constitutes XORing these taps to provide tap(s) back into the register. Linear feedback shift registers have multiple uses in digital systems design.Ī design modeled after LFSRs often has both speed and area advantages over a functionally equivialent design that does not use LFSRs.Īn explanation of how to use LFSRs for these applications can be found in the sales primer for a Linear Feedback Shift Register Megafunction sold by Altera. A Linear Feedback Shift Register is a sequential shift register with combinational logic that causes it to pseudo-randomly cycle through a sequence of binary valuesĪ Linear Feedback Shift Register is a sequential shift register with combinational logic that causes it to pseudo-randomly cycle through a sequence of binary values.

Verilog how to create linear feedback shift register